`timescale 1ns/1ns

module compare_tb;
    reg signed [7:0] i_a;
    reg signed [7:0] i_b;
    wire o_eq,
        o_neq,
        o_gt,
        o_gt_eq,
        o_lt,
        o_lt_eq;

    initial begin
        $dumpfile("output/compare_tb.vcd");
        $dumpvars(0, compare_tb);
    end
    
    initial begin
        #10;
        i_a = 10;
        i_b = 20;
        #10;
        i_a = 15;
        i_b = 10;
        #10;
        i_a = -25;
        i_b = 20;
        #10;
        i_a = -10;
        i_b = -20;
        #10;
        i_a = 80;
        i_b = 90;
        #10;
        i_a = -180;
        i_b = -90;
        #10;
        i_a = 127;
        i_b = 127;
        #10;
        i_a = -128;
        i_b = -127;
        #10;
        i_a = 255;
        i_b = 255;
        #10;
        i_a = -256;
        i_b = -255;
        #100 $stop;
    end
    
    compare compare_inst(
        .iA     (i_a),
        .iB     (i_b),
        .oEQ    (o_eq),
        .oNEQ   (o_neq),
        .oGT    (o_gt),
        .oGT_EQ (o_gt_eq),
        .oLT    (o_lt),
        .oLT_EQ (o_lt_eq)
    );
 
endmodule